The present invention relates generally to integrated circuits, and, more particularly, to a multiple layer integrated circuit having a via structure to improve the routing of the wires within the integrated circuit.
In the field of semiconductor integrated circuits (“ICs”), it is now accepted practice that even though the number of metal layers increases with each technology node, for most designs the silicon density is limited by the amount of available routing resources. Increasing the number of metal layers further will have limited benefit, as all wires to be routed on an upper layer need to pass through a lower layer using a via structure (i.e., a connection structure between wiring planes within an IC), and hence these wires may block via and wiring channels on these layers.